Static Random Access Memory (SRAM) arrays occupy a large fraction of the chip area in many of today's memory designs. As memory will continue to consume a large fraction of many future designs, scaling of memory density involves continuing to track the scaling trends of logic. With transistor and gate length scaling to 45 nanometer (nm) design rule node dimensions and smaller, increased transistor leakage and parameter variation present challenges for the scaling of six transistor (6-T) SRAM cells. As MOSFETs are scaled down, statistical doping fluctuations, oxide thickness variations and line-edge roughness increase the spread in transistor threshold voltage (Vt) which degrades SRAM cell stability and increases the transistor “on” and “off” currents. In order to limit static power dissipation in large caches, lower supply voltages can be used. However, a low supply voltage coupled with large transistor variability further reduces SRAM cell stability. In order to reduce the impact of these variations on devices threshold and memory cell stability, MOSFET devices with channel lengths longer than the particular design rule node dimensions are presently used in the SRAM cell design. This results in larger SRAM cell area which in turn increases the system on a chip device die size and its cost.
In previous approaches, for chip designers to maintain good read/write stability in an SRAM cell as the CMOS technology design rule node dimension is scaled downward, MOSFET transistors with channel lengths longer than the particular design rule have been employed.